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M2006-12A - VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING

Download the M2006-12A datasheet PDF. This datasheet also covers the M20 variant, as both devices belong to the same vcso based fec clock pll with hitless switching family and are provided as variant models within a single manufacturer datasheet.

Description

The M2006-12A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation.

Clock multiplication ratios (including forward and inverse FEC) are pin-selected from pre-programming look-up tables.

Features

  • Reduced intrinsic output jitter and improved power supply noise rejection compared to M2006-12.
  • Similar to the M2006-02A - and pin-compatible - but adds Hitless Switching and Phase Build-out functions.
  • Includes APC pin for Phase Build-out function (for absorption of the input phase change).
  • Pin-selectable PLL divider ratios support forward and inverse FEC ratio translation.
  • Input reference and VCSO frequencies up to 700MHz (Specify VCSO frequency at time of order).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (M20-0612.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number M2006-12A
Manufacturer Integrated Circuit Systems
File Size 419.09 KB
Description VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING
Datasheet download datasheet M2006-12A Datasheet

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Other Datasheets by Integrated Circuit Systems

Part Number Description
M2020 VCSO BASED CLOCK PLL
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M2021 VCSO BASED CLOCK PLL

Full PDF Text Transcription

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Integrated Circuit Systems, Inc. Product Data Sheet M2006-12A VCSO BASED FEC CLOCK PLL WITH HITLESS SWITCHING PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND APC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 GENERAL DESCRIPTION The M2006-12A is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. Clock multiplication ratios (including forward and inverse FEC) are pin-selected from pre-programming look-up tables. Includes Hitless Switching and Phase Build-out to enable SONET (GR-253) / SDH (G.813) MTIE and TDEV compliance during reference clock reselection.
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